sms=axi_master_1, src_tr_width=width_8, sinc=increment, src_msize=length_1
Control Register
| sms | Source master select 0 (axi_master_1): AXI master 1 1 (axi_master_2): AXI master 2 |
| dms | Destination master select |
| sinc | Source address increment 0 (increment): Increment address 1 (nochange): Don’t increment address |
| dinc | Destination address increment |
| src_tr_width | Source transfer width 0 (width_8): 8 bits 1 (width_16): 16 bits 2 (width_32): 32 bits 3 (width_64): 64 bits 4 (width_128): 128 bits 5 (width_256): 256 bits 6 (width_512): 512 bits |
| dst_tr_width | Destination transfer width |
| src_msize | Source burst transaction length 0 (length_1): 1 data item 1 (length_4): 4 data items 2 (length_8): 8 data items 3 (length_16): 16 data items 4 (length_32): 32 data items 5 (length_64): 64 data items 6 (length_128): 128 data items 7 (length_256): 256 data items 8 (length_512): 512 data items 9 (length_1024): 1024 data items |
| dst_msize | Destination burst transaction length |
| nonposted_lastwrite_en | Non Posted Last Write Enable (posted writes may be used till the end of the block) |
| arlen_en | Source burst length enable |
| arlen | Source burst length |
| awlen_en | Destination burst length enable |
| awlen | Destination burst length |
| src_stat_en | Source status enable |
| dst_stat_en | Destination status enable |
| ioc_blktfr | Interrupt completion of block transfer |
| shadowreg_or_lli_last | Last shadow linked list item (indicates shadowreg/LLI content is the last one) |
| shadowreg_or_lli_valid | last shadow linked list item valid (indicate shadowreg/LLI content is valid) |